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Dan Bobyn |
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L1/L2 GPS Receiver Front End Several
L1/L2 GPS Receiver Front Ends have been designed. The latest design incorporated a low noise front end, protective power circuitry for the external active antenna, SAW RF and IF filters and integrated VCO PLL local oscillators along with the usual MMIC RF and IF circuits. The UHF IF signal entering the A/D was sub-sampled to eliminate the second LO. The digitized signal was further processed inside a CPLD to provide radio AGC functions and to format the data samples for export. The CPLD also initialized board functions, including programming all PLL’s which resulted in the board being completely autonomous. This project began with a study phase to identify a suitable receiver architecture. This was followed by a preliminary design activity where the PLL choice and A/D sub-sampling technique were validated. The detailed design phase included all component choice tradeoffs, circuit simulations and schematic design. This was followed by PCB layout, engineering prototypes, design validation and pre-production prototypes. Along
with the prototypes and associated test reports, the client was provided
with the complete drawing package, PCB artworks, BOM details, CPLD code,
engineering design descriptions and manufacturing write-up as a complete
package ready to be transferred to a contract manufacturer for production.
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© 2010 Dan Bobyn Engineering Ltd.